1. Technical Field
The present invention generally relates to computer memory subsystems, and more particularly, to a DRAM (Dynamic Random Access Memory) subsystem in which refresh requests cause the refresh of more than one row or column in the DRAM, but not the entire DRAM.
2. Description of Related Art
DRAM subsystems are well known in the art. They are high density memory subsystems comprised usually of integrated circuits containing millions of memory cells. The density of these types of memories are much higher than those for so-called static memories, but with a disadvantage: the memory cells must be accessed at a certain minimum frequency or data errors will occur due to the limited storage time of the cell.
A typical DRAM cell uses the gate capacitance of one or more field-effect transistors to provide the storage of a binary state. The charge on this capacitor will eventually leak and the DRAM cell may change state, causing an incorrect bit to be set or reset in memory. This problem is typically solved by a refresh scheme which allows the gate of the field-effect transistors to be recharged according to the value stored in the cell, before sufficient discharge has occurred to cause an error.
DRAM circuits are arranged in a 2-dimensional matrix, typically having an equal number of cells in columns and rows. A sense amplifier is attached to each column or row, depending on the organization, which senses the output of a cell being accessed and buffers the value to a usable level for binary output. This sense amplifier output is coupled back to the cell capacitance in order to restore the charge to maintain the correct cell state.
During a refresh cycle, the output of the sense amplifier is fed back to the cell state to the cell input, causing the cell capacitance to be recharged, effectively "refreshing" the voltage on the cell capacitance. Since there is a sense amplifier for each column or row, an entire row or column of the DRAM can be refreshed in one cycle. Therefore, the refresh system only has to go through all the addresses in the other axis in order to completely refresh the DRAM.
The DRAM integrated circuits typically provide an internal counter so that external circuitry is not needed to generate the addresses. So, in order to refresh a modern DRAM, just the RAS (Row Address Select) or CAS (Column Address Select) signal must be pulsed for the number of cells in the opposite axis.
However, the DRAM is unavailable while this operation is occurring, taking system bandwidth because a processor or other memory reading or writing device may have to wait for the refresh cycle to complete. In addition, the overhead associated with acquiring the bus for a refresh cycle--locking out other bus users, is typically significant with respect to the total length of the refresh cycles themselves.
In a typical DRAM memory system, one processor usually has control of the memory at a given time. Address lines and data lines are driven by the processor or buffers attached to the processor address and data signals. In order to cause the processor to release the DRAM for use by other devices, the processor usually provides a "hold" signal and a "hold acknowledge signal." When the "hold" signal is received, the processor has to complete its present operation, which may be quite long if a slow I/O access is being made or a set of instructions that is "locked" is being executed. Locking is an intentional state in which the processor cannot be interrupted and the bus cannot be taken over, to ensure that memory contents are not modified by other devices or other code while that particular sequence of instructions is being executed.
The result of these mechanisms is to create overhead associated with a refresh cycle. The entire overhead is present for every refresh cycle in a system where a single row or column is refreshed at the refresh interval.
One known solution to this problem is use of a burst refresh cycle. In burst refresh of prior systems, the entire DRAM is refreshed at one time, reducing the overhead required to acquire the bus to one acquisition cycle per complete refresh. This has a disadvantage of creating the longest latency for the other devices or processors that need to use the DRAM while the refresh cycle is occurring.
It would, therefore, be desirable to provide a method and system in which DRAM overhead can be optimized against latency of the array to other requests. A system in which the DRAM is partially refreshed would share the overhead of bus acquisition over more than one refresh cycle, but not lock out memory users, such as processors, for long intervals.